1. Field of the Invention
The invention relates to single electron transistors, and more particularly, to a vertical gate-depleted single electron transistor.
2. Description of the Related Art
There has been a trend in the semiconductor industry over the years to reduce device size. However, current technologies are rapidly approaching their limits for further reductions. As a result, single-electron transistors (SETs) have been proposed for further reductions. In SETs, switching operations are performed out using individual electrons, and the SETs can operate at very low voltages.
A vertical gate-depleted single electron transistor has been proposed in the publication: S. Tarucha, D. G. Austing, and T. Honda, Phys. Rev. Lett., 77, 3613 (1996), which publication is incorporated by reference herein. In this structure, the mesa is etched to a point just below the tunneling barrier, and the gate Schottky contact wraps the pillar containing the tunneling barriers. However, this structure makes the fabrication process very complicated.
What is needed is a fabrication process and device structure for vertical gate-depleted single electron transistors that are more simplified and compatible with standard silicon processes used by industry. The present invention satisfies that need.